1. Field of the Invention
The present invention generally relates to a successive approximation register (SAR) analog-to-digital converter (ADC), and more particularly to a SAR ADC with a window predictive function.
2. Description of Related Art
A successive approximation register (SAR) analog-to-digital converter (ADC) is a type of ADC that converts an analog signal to a digital equivalent of the signal. The SAR ADC performs conversion by comparison and searching through all possible quantization levels to obtain a digital output. The SAR ADC requires less silicon area and the associated cost than other ADC architectures. However, the SAR ADC needs more cycles to obtain the digital output, and therefore does not fit for high speed applications.
Some conventional methods are proposed to speed up the operation of the SAR ADC. One of the conventional methods is to tolerate settling error in phases of comparison, however, at the cost of its linearity.
Moreover, although the SAR ADC consumes less power than other ADC architectures, its power consumption is still too high to be adapted to some electronic devices that has limited power source.
For the foregoing reasons, a need has arisen to propose a novel SAR ADC that can speed up the operation without sacrificing its linearity.